A Novel VLSI based Architecture for Computation of 2D-DCT Image Compression

Data image compression is the reduction of redundancy in data representation in order to achieve reduction in storage cost. In This paper The Implementation and Optimization of FPGA based 2DDCT (discrete Cosine Transform) with Quantization and Zigzag with parallel pipelining using VHDL. The two 1D-DCT Separability property and calculation by using a Transpose buffer .The coding is simulated using Xilinx 9.2i ISE Synthesized using Spartan-3E XC3S500. The 2D-DCT Architecture uses 615 slices, 74 I/O pins, and 6 multiplier and operating frequency 124MHz and pipeline latency 160 clock cycles. Keyword: JPEG, discrete cosine transform (DCT), quantization, zigzag, FPGA, model Sim